Ph.D., Computer Science and Engineering, August 2006
Dissertation: Traveling Threads: A New Multithreaded Execution Model
Advisor: Peter M. Kogge


Masters of Science in Computer Science and Engineering, May 2000
Thesis: Design Parameters for Distributed PIM Memory Systems
Advisor: Peter M. Kogge


Bachelors of Science, May 1998
Computer Science


Bachelors of Arts, May 1998
Government and International Studies (Political Science as of 2003)
Honors Thesis: British Constitutional Reform: Sovereignty, Economics, and Party Politics
Advisor: Andrew C. Gould

Professional Experience

Gem State Informatics, Inc., Co-founder and CEO (September 2020-Present), Boise, ID

MICRON TECHNOLOGY, INC, Director of Advanced Computing Solutions Pathfinding (November 2012-September 2020), Boise, ID

Lead the discover and road-mapping effort for new classes of advanced memory systems, particularly Processor-In-Memory (PIM) systems.  Explore industry (internal and joint development) and government sponsored (DOE, DOD, DARPA) R&D efforts.

SANDIA NATIONAL LABORATORIES, Principal Member of Technical Staff (March 2006-November 2012) , Albuquerque, NM

Helped to establish the computer architecture research program at Sandia and served as Principal Investigator for multiple DOE, DOD, and DARPA programs including Sandia’s Extreme-Scale Computing Grand Challenge, DARPA UHPC Program (X-caliber), Processing-In-Memory (PIM) research, Sandia Secure Processor Program for defense of cyberphysical systems, R&D into advanced CPUs for cybersecurity, and novel memory and CPU architectures for supercomputers. Advised IARPA and DARPA on establishment of these programs.  Served as co-PI for NSF’s “PXGL: Cyberinfrastructure for Scalable Graph Execution”, Large Research Collaboration Award #1111798, August 2011.

In these roles, led a multidisciplinary research team of over 30 senior researchers with multiple academic and industry institutions as partners.  Served as a member for the first steering committee for the DOE Institute for Advanced Architecture after it was created by Congress.  Research areas in advanced memory architectures and PIM, focused on an application driven computer architecture.

SANDIA NATIONAL LABORATORIES, Intern (May-August 2003, and May-October 2004), Albuquerque, NM

Performed simulation and analysis of real-world applications for traveling thread and PIM based architectures that formed the basis for my dissertation.

SUN MICROSYSTEMS, INC, Member of Technical Staff (2000-2002), San Diego, CA

Project Lead or Technical Lead in the Enterprise Server Products division.  Conducted research into dynamic hardware reconfiguration, system workload modeling, large memory architectures, and operating systems for high-end (E10k,  F15k) and midframe (Fx800) systems.  Served as an architect for Sun’s N1 effort.

QUALCOMM INC, Engineering Intern (1995-1998), San Diego, CA

Network programming and large-scale data analysis.

Academic Appointments

Honors, Awards, and Professional Societies

Advisory Boards

  • Convey Computer Corporation, Richardson TX,  2012-2014

Patents and Disclosures

  1. Tim Finkbeiner, Glen Hush, and Richard Murphy, Apparatuses and Methods for Determining Population Count, US Patent 20,160,062,692
  2. Troy Manning and Richard Murphy, Apparatuses and Methods for Parity Determination Using Sensing Circuitry, US Patent 20,150,357,007
  3. Troy Manning and Richard Murphy, Apparatuses and Methods for Performing Logical Operations Using Sensing Circuitry, US Patent 20,150,357,008
  4. Wheeler, Kyle, Troy Manning, and Richard Murphy, Comparison Operations in Memory, US Patent 20,150,357,019
  5. Murphy, Richard C. and Troy Manning Memory Mapping, US Patent 20,150,270,015
  6. Murphy, Richard C., Memory Controlled Data Movement and Timing, US Patent Application 13/935,303.
  7. Underwood, Keith D., Arun F. Rodrigues, Peter M. Kogge, and Richard C. Murphy, Intra-Cache Line Gather/Scatter, Submitted to the USPTO 2/12/2008
  8. Murphy, Richard C., Automated Resource Management Using Perceptron Prediction, US Patent 7,191,329
  9. Murphy, Richard C., Scott Carter, Shrikant Deshpande, and Mario Ornelas, System and Method for Dynamic Resource Reconfiguration Using a Dependency Graph, US Patent 7,152,157

Open Source Software Contributions

Refereed Journal Articles

  1. Rajeev Balasubramonian, Jichuan Chang, Troy Manning, Jaime Moreno, Richard Murphy, Ravi Nair, and Steven Swanson, Near Data Processing Insights, IEEE Micro 34(4), p36-42, July 2014
  2. Murphy, Richard C., Sterling, Thomas, and Chirag Dekate, Advanced Architectures and Execution Models to Support Green Computing, Computing in Science and Engineering 12(6), p38-47, November 2010
  3. Alvin, Ken, Brian Barrett, Ron Brightwell, Sudip Dosanjh, Al Geist, Scott Hemmert, Mike Heroux, Doug Kothe, Richard Murphy, Jeff Nichols, Ron Oldfield, Arun Rodrigues, and Jeffrey Vetter, On the Path to Exascale, International Journal of Distributed Systems and Technologies (IJDST) 1(2), p1-22, April, 2010
  4. Murphy, Richard C., DOE’s Institute for Advanced Architecture and Algorithms: an Application-Driven Approach, Journal of Physics Conference Series 180(2009), 012044
  5. Murphy, Richard C. and Peter M. Kogge, On the Memory Access Patterns of Supercomputer Applications: Benchmark Selection and Its Implications, IEEE Transactions on Computers 56(7): 937-945, July 2007

Refereed Conferences and Workshops with Proceedings

  1. Wheeler, Kyle, Richard Murphy, Dylan Stark, and Brad Chamberlain, The Chapel Tasking Layer over Qthreads, CUG, Fairbanks, Alaska, May 23-26, 2011
  2. Murphy, Richard, Kyle Wheeler, Brian Barrett, and Jim Ang, Introducing the Graph500, CUG, Edinburgh, Scotland, May 24-27, 2010
  3. Hu, X. Sharon, Richard C. Murphy, Sudip Dosanjh, Kunle Olukoton, Steve Poole, Hardware/Software Co-Design for High Performance Computing, CODES+ISSS’10, October 24, 2010
  4. Wheeler, Kyle, Douglas Thain, and Richard Murphy, Portable Performance from Workstation to Supercomputer: Distributing Data Structures with Qthreads, Proceedings of the First Workshop on Programming Models for Emerging Architectures, Pages 1-8, September 2009
  5. Barrett, Brian W., and Jonathan W. Berry, Richard C. Murphy, and Kyle B. Wheeler, Implementing a Portable Multi-threaded Graph Library: the MTGL on Qthreads, International Parallel and Distributed Processing Symposium 2009 (IPDPS09), Rome, Italy, Pages 1-8, May 2009
  6. Wheeler, Kyle, Richard C. Murphy, and Douglas Thain, Qthreads: An API for Programming with Millions of Lightweight Threads in the Proceedings of the Workshop on Multithreaded Architectures and Applications, Miami, FL, 2008
  7. Murphy, Richard C. On the Effects of Memory Latency and Bandwidth on Supercomputer Application Performance in the Proceedings of the IEEE International Symposium on Workload Characterization 2007 (IISWC07), Boston, MA, September 27-29, 2007
  8. Rodrigues, Arun F., Richard C. Murphy, Peter Kogge, and Keith Underwood, The Structural Simulation Toolkit: Exploring Novel Architectures, Proceedings of Supercomputing 2006 (SC06)
  9. Murphy, Richard C., Jonathan Berry, William McLendon, Bruce Hendrickson, Douglas Gregor and Andrew Lumsdaine, DFS: A Simple to Write Yet Difficult to Execute Benchmark in the Proceedings of the 2006 IEEE International Symposium on Workload Characterization, San Jose, CA, October 25-27, 2006
  10. Sridharan, Srinivas, Brett Keck, Richard Murphy, Surendar Chandra, and Peter Kogge, Thread Migration to Improve  Synchronization Performance in the Proceedings of the 2006 Workshop on Operating Systems Interference in High Performance Applications (OSIHPA 2006), in conjunction with PACT 2006, Seattle, WA, September 17, 2006
  11. Murphy, Richard C., Arun Rodrigues, Peter Kogge, and Keith Underwood, The Implications of Working Set Analysis on Supercomputing Memory Hierarchy Design in the Proceedings of the 2005 International Conference on Supercomputing, Cambridge, MA, June 20-22, 2005
  12. Underwood, Keith D., K. Scott Hemmert, Arun Rodrigues, Richard Murphy, and Ron Brightwell, A Hardware Acceleration Unit for MPI Queue Processing, in the Proceedings of the 19th International Parallel and Distributed Processing Symposium, Denver, CO, April  4-8, 2005
  13. Rodrigues, Arun, Richard Murphy, Ron Brightwell, and Keith D. Underwood, Enhancing NIC Performance for MPI using Processing-in-Memory, in the Proceedings of the 2005 Workshop on Communication Architectures for Clusters, in conjunction with IPDPS, Denver, CO, April 4-8, 2005
  14. Rodrigues, Arun, Richard Murphy, Peter Kogge, and Keith Underwood, Characterizing a New Class of Threads in Scientific Applications for High End Supercomputers, in the Proceedings of the 18th Annual ACM International Conference on Supercomputing, June 26-July 1 2004, Saint Malo, France
  15. Antonelli, Dominic A., Timothy J. Dysart, Danny Z. Chen, Xiaobo S. Hu, Andrew B. Kahng, Peter M. Kogge, Richard C. Murphy, and Michael T. Niemier, Quantum-Dot Cellular Automata (QCA) Circuit Partitioning: Problem Modeling and Solutions, in the Proceedings of the 41st Design Automation Conference, June 7-11, 2004, San Diego, CA.
  16. Rodrigues, Arun, Richard C. Murphy, Peter M. Kogge, Jay Brockman, Ron Brightwell, and Keith Underwood Implications of a PIM Architectural Model for MPI, IEEE International Conference on Cluster Computing, Tsim Sha Tsui, Kowloon, Hong Kong, December 1-4, 2003
  17. Murphy, Richard C. Phrase Detection and the Associative Memory Neural Network in the Proceedings of the 2003 International  Joint Conference on Neural Networks, Portland Oregon, July 20-24, 2003
  18. Murphy, Richard C. and Peter M. Kogge, Trading Bandwidth for Latency: Managing Continuations Through a Carpet Bag Cache in the Proceedings of the International Workshop on Innovative Architecture 2002 (IWIA02), Jan. 10-11, 2002
  19. Kuntz, Shannon K., Richard C. Murphy, Michael T. Niemier, Jesus Izaguirre, and Peter M. Kogge,  Petaflop Computing for Protein Folding,Tenth SIAM Conference on Parallel Processing for Scientific Computing, Portsmouth, Virginia, March 12-14, 2001
  20. Murphy, Richard C., Peter M. Kogge, and Arun Rodrigues, The Characterization of Data Intensive Memory Workloads on Distributed PIM Systems, in the proceedings of the Second Workshop on Intelligent Memory Systems, held in conjunction with ASPLOS-IX, Cambridge, MA November 12-15, 2000 (Lecture Notes in Computer Science 2107, Springer-Verlag, November 2001)

Technical Reports

  1. Stark, Dylan, Kyle Wheeler, and Richard Murphy, A Comparative Critical Analysis of Modern Task-Parallel Runtimes, Sandia Technical Report (SAND2012-10594)
  2. Murphy, Richard C., Building More Powerful Less Expensive Supercomputers Using Processing-In-Memory (PIM) LDRD Final Report, Sandia Technical Report (SAND2009-6229)
  3. Murphy, Richard C., Workshop on Programming Languages for High Performance Computing (HPCWPL) Final Report, Sandia Technical Report (SAND2007-2047)

Invited Talks

  1. Innovation while Facing the End of Moore’s Law, Keynote Micron DPTS, September 16, 2015
  2. Opportunities in Memory to Support Advanced Graph Analytics, DARPA Graph Workshop, October 8, 2013
  3. Keynote: Custom is the New Commodity, LexisNexis/HPCC Systems Technical Summit, September 10-12, 2013
  4. Optical Interconnects for Advanced Memory Modules: From Disaggregated Racks to Full Datacenter Computers, IEEE Photonics Society Summer Topicals 2013, July 8-10, 2013
  5. Through the Exascale Looking-Glass and What Alice Found There, DOE/ASCR Architecture Conference,  Palo Alto, CA, August 2-3, 2011
  6. How I Learned to Stop Worrying and Love New Models of Computation, DOE Office of Science Programming Methods Workshop, Marina Del Rey, CA, July 27-29, 2011
  7. X-caliber Supercomputer, HPCC Conference, Newport, RI, March 28-31, 2011
  8. Getting Ready for Hybrid Multicore Computing or On Data Movement Pico Joules and Codesign (oh my!), Advanced Scientific Computing Advisory Committee Meeting (ASCAC), Washington, DC, March 21-22, 2011
  9. Graph 500: Creating an International Benchmark (and competition!) for Data Intensive Computing, SOS 15 Workshop Engelberg, Switzerland, March 14-17, 2011
  10. Data Intensive Computing and the Graph500, HPC User Forum, Seattle, WA, September 13-15, 2010.
  11. The X-caliber Architecture for Informatics Supercomputers, Salishan Conference on High Speed Computing, Gleneden Beach, OR, April 26-30, 2010
  12. Enabling Architectures for Large-Scale Applications, CCC Future of Computer Architecture Workshop, San Diego, CA, February 21-23, 2010
  13. DOE’s Institute for Advanced Architecture and Algorithms: an Application-Driven Approach, SciDAC 2009, San Diego, CA, June 14-18, 2009
  14. Data Movement Dominates: An Application-Centric View of High Performance Interconnects, HSD 2009 20th Annual Workshop on Interconnects Within High Speed Digital Systems, Santa Fe, NM, May 3-6, 2009
  15. Can We Continue to Build Supercomputers Out of Processors Optimized for Laptops?, 13th Workshop on Distributed Supercomputing (SOS 13), Hilton Head, SC, March 9-12, 2009
  16. Initial Thoughts on Cortex Scale Supercomputer Simulations, DARPA Electronic Cortex Workshop, Arlington, VA, August 2, 2007
  17. (with Bruce Hendrickson and Keith Underwood) How Relevant is Computer Architecture Research to Emerging Memory Intensive Applications? CRA Conference on Grand Research Challenges held December 4-7, 2005 in Monterey, CA
  18. Traveling Threads: A New Multithreaded Execution Model, Oak Ridge National Lab, December 6, 2005
  19. Traveling Threads: A New Multithreaded Execution Model, Sandia National Lab, April 11, 2005
  20. Processing-In-Memory: Technology, Execution Model, Architecture, and Traveling Threads, Conference on High Speed Computing, Salishan Lodge, Gleneden Beach, OR, April 21-24, 2003.

Teaching Experience

  • Primary Instructor, CS441, Computer Architecture (undergraduate), BSU, Fall 2014, Fall 2016
  • Primary Instructor, EE590, New Mexico State University, Selected Topics in Memory Architecture: co-taught and designed a graduate topics course on advanced memory systems, Spring 2010
  • Primary Instructor, EE564, New Mexico State University, Advanced Computer Architecture: Graduate-level computer architecture course, Fall of 2010 and 2011
  • Primary Instructor CSE321 and CSE321(L): Notre Dame’s first semester computer architecture course, Fall of 2002 and 2003.

Professional Activities and Service

  1. Chair (and Founder), Graph500 Benchmark Executive Committee, June 2010-Present
  2. Organizing Committee, Chesapeake Large Scale Analytics Conferences (CLSAC), 2012-Present
  3. Program Committee Member, IEEE International Parallel and Distributed Processing Symposium (IPDPS) Architecture Track 2017, IPDPS 2017
  4. Chair, Student Program Fundraising, Supercomputing 2016
  5. Chair, Student Job fare, Supercomputing 2015
  6. Deputy Chair, Student Volunteers, Supercomputing 2013-2014.
  7. Program Committee Member, Workshop on Near Memory Processing (in conjunction with IEEE Micro), 2013.
  8. Steering Committee Member, DOE Institute for Advanced Architecture and Algorithms, 2007-2012.
  9. Program Committee Member, IEEE International Parallel and Distributed Processing Symposium (IPDPS) Architecture Track 2010.
  10. Organizing Committee Member, Salishan Conference on High Speed Computing, Salishan Lodge, Glenden Beach, OR, 2008-2009
  11. Program Committee Member, International Conference on Parallel Processing (ICPP) 2007, 2008, 2009
  12. Organizing Committee Chair, Sandia Workshop on Memory Opportunities for High Performance Computing, Albuquerque, NM 2007
  13. Program Committee Chair and Steering Committee Member Workshop on Programming Languages for High Performance Computing (HPCWPL), December 12-13, 2006, Albuquerque, NM.